Insuperjunction with surrounding lightly doped drain region

ABSTRACT

A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of U.S. patent application Ser.No. 15/080,807 filed Mar. 25, 2016, now U.S. Pat. No. 10,199,459, whichapplication is a continuation-in-part of U.S. patent application Ser.No. 14/333,323, now U.S. Pat. No. 9,299,774, filed Jul. 16, 2014, andclaims the benefit of U.S. Provisional Application No. 61/856,631, filedJul. 19, 2013 and U.S. Provisional Application No. 61/857,193, filedJul. 22, 2013, which applications are all incorporated herein byreference in their entirety.

BACKGROUND

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Discrete semiconductor devices generally contain one type ofelectrical component, e.g., light emitting diode (LED), small signaltransistor, resistor, capacitor, inductor, and power metal oxidesemiconductor field effect transistor (MOSFET). Integrated semiconductordevices typically contain hundreds to millions of electrical components.Examples of integrated semiconductor devices include microcontrollers,microprocessors, charged-coupled devices (CODs), solar cells, anddigital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as signalprocessing, high-speed calculations, transmitting and receivingelectromagnetic signals, controlling electronic devices, transformingsunlight to electricity, and creating visual projections for televisiondisplays. Semiconductor devices are found in the fields ofentertainment, communications, power conversion, networks, computers,and consumer products. Semiconductor devices are also found in militaryapplications, aviation, automotive, industrial controllers, and officeequipment. In particular, power MOSFETs are commonly used in electroniccircuits, such as communication systems and power supplies, as electricswitches to enable and disable the conduction of relatively largecurrents in DC to DC converter applications.

A power MOSFET device includes a large number of MOSFET cells orindividual transistors that are connected in parallel and distributedacross a surface of a semiconductor die. Power MOSFET devices aretypically used as electronic switches to control power flow to acircuit. A control signal at a gate terminal of the power MOSFETcontrols whether current flows through the MOSFET between a drainterminal and source terminal of the MOSFET. The conduction path betweenthe drain terminal and source terminal of a MOSFET is wired in serieswith a circuit to be switched, so that when the MOSFET is off, i.e., theMOSFET limits current between the source and drain terminals, current isalso limited through the switched circuit. When the MOSFET is on,current flows through the MOSFET and the switched circuit to power theswitched circuit.

Power MOSFETs waste energy through switching power loss and conductionpower loss. Conduction losses are proportional to the effectiveresistance of the conduction path from the drain terminal to the sourceterminal when the transistor is turned on (RDSON), i.e., the resistanceexhibited for current flowing to powered circuits. A MOSFET with ahigher RDSON will absorb more energy, and generate more heat, as currentflows through the MOSFET to the circuit being powered.

Switching losses are proportional to the switching frequency andinternal parasitic capacitance, most significantly gate to draincapacitance (Cgd). A higher Cgd indicates more energy is used in orderto switch a MOSFET from on to off, or from off to on. The gate charge ofa MOSFET (Qg) indicates the amount of charge supplied to the gateterminal to switch a MOSFET on. Qg is proportional to the Cgd of aMOSFET. Frequency of switching increases switching loss because thepower loss experienced during a single switch cycle is experienced moreoften.

One goal of power MOSFET manufacturers is to produce power MOSFETdevices with lower conduction losses. Lower conduction loss, i.e., lowerRDSON, reduces the amount of energy absorbed by the power MOSFET whenthe MOSFET is conducting. When a power MOSFET absorbs energy, moreenergy is required to power the circuit as a whole. In addition, theabsorbed energy is released by the MOSFET as thermal energy which mayneed to be dissipated away from the MOSFET using a heatsink, or othermethod, to prevent damage to the MOSFET.

Another goal of power MOSFET manufacturers is to produce power MOSFETdevices which can switch higher voltage power signals. In order toswitch a power signal of a certain voltage level, a power MOSFETsustains an equivalent voltage between the drain terminal and sourceterminal when off. The maximum voltage level which a power MOSFET can beused with is determined by the BVdss value of the MOSFET, or the maximumblocking voltage of the MOSFET between drain and source.

Conventional power MOSFETs use a vertical or trench configuration due toa characteristically low RDSON. However, trench power MOSFETS commonlyexhibit high Cgd and Qg, which results in a higher switching power loss.The trench MOSFET structure can be modified to improve Cgd, but at theexpense of significantly increased manufacturing complexity. On theother hand, lateral double-diffused MOSFETs (LDMOS) offer inherentlylower Qg than vertical double-diffused power MOSFETS (VDMOS), whichreduces switching power loss, but have a higher RDSON, which increasesconduction power loss.

Conventional power MOSFETs include a lightly doped drain (LDD), ordrift, region to support a higher BVdss. FIG. 1a illustrates aconventional N-channel LDMOS power MOSFET cell 10. MOSFET cell 10 isformed from P-doped base substrate material 12, and includes P-channelarea 14, P+ source contact region 16, N+ source contact region 18, andN+ drain contact region 20. Gate dielectric 22 is formed over basesubstrate material 12, and polysilicon (poly) gate 24 is formed over thegate dielectric. LDD region 26 is lightly doped with an N-type dopantand runs from an area under poly gate 24 to N+ drain contact region 20.

The doping concentration of LDD region 26 has an inverse relationship toBVdss, but also has an inverse relationship to RDSON. Lowering thedoping concentration of LDD region 26 results in MOSFET cell 10 having ahigher BVdss, but also a higher RDSON. The LDD region supports a highBVdss of MOSFET cell 10 by providing additional area between a voltageapplied to the MOSFET at N+ drain contact region 20 and the channelunder poly gate 24. The additional area, combined with a lower dopingconcentration, provided by LDD region 26 spreads out a depletion regionbetween the applied voltage at N+ drain contact region 20 and thechannel under poly gate 24 to produce a lower magnitude electric fieldfor a given voltage, thereby increasing BVdss. While LDD region 26results in a reduced electric field, fixed potential points exist at theedge of poly gate 24 and at N+ drain contact region 20 which cause theelectric field to peak at each end of the LDD region.

A depletion region exists at the boundary between LDD region 26 and basesubstrate material 12. As a voltage applied to N+ drain contact region20 rises, the depletion region between LDD region 26 and base substratematerial 12 grows. The doping of LDD region 26 is such that LDD region26 will be fully depleted of charge carriers prior to MOSFET cell 10breaking down. Base substrate material 12 is more lightly doped than LDDregion 26, and the depletion region extends further into the basesubstrate material than the size of the LDD region.

Power MOSFET manufacturers want to create devices with lower RDSON, andhave developed superjunction structures used as the drift region of aMOSFET cell, instead of an LDD region, to reduce RDSON. FIG. 1billustrates MOSFET cell 30 which utilizes a superjunction drift region.MOSFET cell 30 is formed in a similar process to MOSFET cell 10 in FIG.1a , but N-doped stripes 32 and P-doped stripes 34 are formed to replaceLDD region 26. N-doped stripes 32 include a width Wn. P-doped stripes 34include a width Wp. Stripes 32 and 34 include a junction depth into basesubstrate material 12, Xj, which is the same for each stripe. Stripes 32and 34 are doped as heavily as possible while still fully depletingprior to the breakdown of MOSFET cell 30. A superjunction is used toprovide as much heavily doped area between N+ drain contact region 20and poly gate 24 as possible.

Superjunctions remove the relationship between BVdss and dopingconcentration, as is the case with MOSFET cell 10 which uses LDD region26. A higher doping concentration is used in the superjunction ascompared to LDD region 26, resulting in lower RDSON. MOSFETs designedwith a superjunction improve the RDSON of the MOSFET without asignificant increase in Qg, resulting in a net reduction of total powerloss.

Superjunctions maintain a high BVdss despite a high doping concentrationby replacing the depletion region between LDD region 26 and basesubstrate material 12 with a plurality of depletion regions between eachadjacent N-doped stripe 32 and P-doped stripe 34. Stripes 32 and 34deplete each other instead of base substrate material 12, therefore theelectric field of the superjunction is oriented laterally. The dopingconcentrations of stripes 32 and 34 are calibrated such that the stripesfully deplete prior to breakdown of MOSFET cell 30, similarly to LDDregion 26 in MOSFET cell 10. After stripes 32 and 34 are fully depleted,the voltage at drain contact region 20 is supported by the length, Lsj,of the superjunction. When the superjunction is fully depleted, theelectric field from applied voltage at N+ drain contact 20 to poly gate24 is oriented lengthwise through the superjunction. Making stripes 32and 34 longer increases BVdss by stretching the electric fields over alonger distance, reducing the magnitude of the electric fields.

N-doped stripes 32 and P-doped stripes 34 include strong electric fieldsat the depletion regions between the stripes. In addition, as with LDDregion 26, inherently stronger electric fields exist under the edge ofpoly gate 24 and at N+ drain contact region 20. The strong electricfields of the depletion regions between N-doped stripes 32 and P-dopedstripes 34 combine with the electric field peaks at the edge of polygate 24 and N+ drain contact region 20 to create an electric fieldstrong enough to cause breakdown of MOSFET cell 30 at a lower voltagethan is desired.

The strong electric fields of the superjunction depletion regionscombining with the electric field peaks at poly gate 24 and N+ draincontact region 20 also creates hot carriers. Hot carriers are electronsor holes which reach an energy high enough to be injected intodielectric layer 22. Hot carriers trapped in dielectric layer 22increase leakage current through the dielectric layer, and eventuallylead to a short circuit between poly gate 24 and base substrate material12. Hot carriers trapped in dielectric layer 22 also create an electricfield in base substrate material 12 and disrupt the charge balance ofthe superjunction. BVdss is reduced by hot carriers affecting the chargebalance of the superjunction.

Thinner stripes 32 and 34 are doped at a higher concentration whilestill fully depleting at the same voltage as thicker superjunctionstripes. In addition, using thinner stripes 32 and 34 does not reducethe total conduction area through N-doped stripes 32 when MOSFET cell 30is on because the area through the N-doped stripes is approximately halfof the total width of the MOSFET regardless of the width of eachindividual stripe. Therefore, thinner stripes 32 and 34 benefit totalRDSON without hurting BVdss.

Forming deeper stripes 32 and 34 reduces RDSON by providing moreconduction area for current through MOSFET cell 30 when the MOSFET ison. However, fabricating a deep superjunction LDMOS requires high energyion implants, a trench etch with sidewall implant, or a multi-stepsilicon epitaxy. Each option for fabricating a deep superjunctionpresents challenges in terms of cost, process engineering, and processequipment capability. Fabricating a deep junction with narrow stripewidths using conventional implant and well techniques is challengingbecause the thermal diffusion processes required to form deep wellscause the N and P stripes to diffuse together, which reduces oreliminates the benefits of a superjunction. Using a high resolutionphotoresist is challenging because as resolution of the photoresist isincreased, thickness is decreased. The thin photoresist required forhigh resolution ion implants does not easily block the high energy ionimplants required to form deep junctions.

FIG. 1c illustrates the theoretical relationship between stripe width,junction depth, and RDSON. FIG. 1c shows that RDSON is reduced as stripewidth (Wn and Wp) is reduced, and as junction depth (Xj) is increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1c illustrate conventional power MOSFETs;

FIG. 2 illustrates a printed circuit board (PCB) with different types ofpackages mounted to a surface of the PCB;

FIGS. 3a-3d illustrate a semiconductor wafer with a plurality ofsemiconductor die separated by a saw street;

FIGS. 4a-4p illustrate a soft mask method of forming a power MOSFETutilizing a superjunction with surrounding LDD region;

FIGS. 5a-5h illustrate a hard mask method of forming a power MOSFETutilizing a superjunction with surrounding LDD region;

FIGS. 6a-6k illustrate a hard mask method of forming a power MOSFETutilizing a self-aligned superjunction with surrounding LDD region;

FIG. 7 illustrates a power MOSFET utilizing a superjunction withsurrounding LDD region formed with N-doped stripes extending through anN+ doped drain contact region;

FIG. 8 illustrates a power MOSFET utilizing a superjunction withsurrounding LDD region formed with a source trench;

FIG. 9 illustrates a power MOSFET utilizing a superjunction withsurrounding LDD region and field plates;

FIGS. 10a-10c illustrate biasing the superjunction by laterallyextending P-doped stripes of the superjunction under the gate of theMOSFET cell; and

FIGS. 11a-11e illustrate biasing the superjunction by verticallyextending P-doped stripes of the superjunction under the surrounding LDDregion.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving objectives of theinvention, those skilled in the art will appreciate that the disclosureis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and claims equivalents as supported by the followingdisclosure and drawings.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors and diodes, have the abilityto control the flow of electrical current. Passive electricalcomponents, such as capacitors, inductors, and resistors, create arelationship between voltage and current necessary to perform electricalcircuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devicesby dynamically changing the semiconductor material conductivity inresponse to an electric field or base current. Transistors containregions of varying types and degrees of doping arranged as necessary toenable the transistor to promote or restrict the flow of electricalcurrent upon the application of the electric field or base current.

A region of a semiconductor wafer can be negatively doped or positivelydoped. Negatively doped, or N-doped, regions are doped with a negative,or N-type, dopant, such as phosphorus, antimony, or arsenic. Eachmolecule of an N-type dopant contributes an additional negative carrier,i.e., an electron, to the semiconductor wafer. Positively doped, orP-doped, regions are doped with a positive, or P-type, dopant such asboron, aluminum, or gallium. Each molecule of P-type dopant contributesan additional positive carrier, i.e. a hole, to the semiconductor wafer.A region of one doping type can be made into a region of the otherdoping type by adding dopant of the second type in excess of theexisting doping concentration. N-type and P-type regions are oppositelydoped.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition can involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual semiconductor die and packaging thesemiconductor die for structural support, electrical interconnect, andenvironmental isolation. To singulate the semiconductor die, the waferis scored and broken along non-functional regions of the wafer calledsaw streets or scribes. The wafer is singulated using a laser cuttingtool or saw blade. After singulation, the individual semiconductor dieare mounted to a package substrate that includes pins or contact padsfor interconnection with other system components. Contact pads formedover the semiconductor die are then connected to contact pads within thepackage. The electrical connections can be made with conductive layers,bumps, stud bumps, conductive paste, or wirebonds. An encapsulant orother molding material is deposited over the package to provide physicalsupport and electrical isolation. The finished package is then insertedinto an electrical system and the functionality of the semiconductordevice is made available to the other system components.

FIG. 2 illustrates electronic device 50 having a chip carrier substrateor PCB 52 with a plurality of semiconductor packages mounted on asurface of PCB 52. Electronic device 50 can have one type ofsemiconductor package, or multiple types of semiconductor packages,depending on the application. The different types of semiconductorpackages are shown in FIG. 2 for purposes of illustration.

Electronic device 50 can be a stand-alone system that uses thesemiconductor packages to perform one or more electrical functions.Alternatively, electronic device 50 can be a subcomponent of a largersystem. For example, electronic device 50 can be part of a tablet,cellular phone, digital camera, or other electronic device.Alternatively, electronic device 50 can be a graphics card, networkinterface card, or other signal processing card that can be insertedinto a computer. The semiconductor package can include microprocessors,memories, application specific integrated circuits (ASIC), logiccircuits, analog circuits, radio frequency (RF) circuits, discretedevices, or other semiconductor die or electrical components.Miniaturization and weight reduction are essential for the products tobe accepted by the market. The distance between semiconductor devicesmay be decreased to achieve higher density.

In FIG. 2, PCB 52 provides a general substrate for structural supportand electrical interconnect of the semiconductor packages mounted on thePCB. Conductive signal traces 54 are formed over a surface or withinlayers of PCB 52 using evaporation, electrolytic plating, electrolessplating, screen printing, or other suitable metal deposition process.Signal traces 54 provide for electrical communication between each ofthe semiconductor packages, mounted components, and other externalsystem components. Traces 54 also provide power and ground connectionsto each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels.First level packaging is a technique for mechanically and electricallyattaching the semiconductor die to an intermediate substrate. Secondlevel packaging involves mechanically and electrically attaching theintermediate substrate to the PCB. In other embodiments, a semiconductordevice may only have the first level packaging where the die ismechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging,including bond wire package 56 and flipchip 58, are shown on PCB 52.Additionally, several types of second level packaging, including ballgrid array (BGA) 60, bump chip carrier (BCC) 62, land grid array (LGA)66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70,quad flat package 72, embedded wafer level ball grid array (eWLB) 74,and wafer level chip scale package (WLCSP) 76 are shown mounted on PCB52. In one embodiment, eWLB 74 is a fan-out wafer level package (Fo-WLP)and WLCSP 76 is a fan-in wafer level package (Fi-WLP). Depending uponthe system requirements, any combination of semiconductor packages,configured with any combination of first and second level packagingstyles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device 50 includes a single attachedsemiconductor package, while other embodiments call for multipleinterconnected packages. By combining one or more semiconductor packagesover a single substrate, manufacturers can incorporate pre-madecomponents into electronic devices and systems. Because thesemiconductor packages include sophisticated functionality, electronicdevices can be manufactured using less expensive components and astreamlined manufacturing process. The resulting devices are less likelyto fail and less expensive to manufacture resulting in a lower cost forconsumers.

FIG. 3a shows a semiconductor wafer 120 with a base substrate material122, such as silicon, germanium, aluminum phosphide, aluminum arsenide,gallium arsenide, gallium nitride, indium phosphide, silicon carbide, orother bulk semiconductor material for structural support. A plurality ofsemiconductor die or components 124 is formed on wafer 120 separated bya non-active, inter-die wafer area or saw street 126 as described above.Saw street 126 provides cutting areas to singulate semiconductor wafer120 into individual semiconductor die 124. In one embodiment,semiconductor wafer 120 has a width or diameter of 200-300 millimeters(mm). In another embodiment, semiconductor wafer 120 has a width ordiameter of 100-450 mm.

FIG. 3b shows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die 124 has a back or non-active surface 128 andan active surface 130 containing analog or digital circuits implementedas active devices, passive devices, conductive layers, and dielectriclayers formed within the die and electrically interconnected accordingto the electrical design and function of the die. For example, thecircuit may include one or more transistors, diodes, and other circuitelements formed within active surface 130 to implement analog circuitsor digital circuits, such as digital signal processor (DSP), ASIC,memory, or other signal processing circuit. Semiconductor die 124 mayalso contain integrated passive devices (IPDs), such as inductors,capacitors, and resistors, for RF signal processing.

An electrically conductive layer 132 is formed over active surface 130using PVD, CVD, electrolytic plating, electroless plating process, orother suitable metal deposition process. Conductive layer 132 can be oneor more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni),gold (Au), silver (Ag), titanium (Ti) or other suitable electricallyconductive material. In one embodiment, Ti is formed over Al bysputtering for later Cu plating. Other metal layers compatible with Cuplating can also be used to form conductive layer 132. Conductive layer132 operates as contact pads electrically connected to the circuits onactive surface 130. Conductive layer 132 can be formed as contact padsdisposed side-by-side a first distance from the edge of semiconductordie 124, as shown in FIG. 3b . Alternatively, conductive layer 132 canbe formed as contact pads that are offset in multiple rows such that afirst row of contact pads is disposed a first distance from the edge ofthe die, and a second row of contact pads alternating with the first rowis disposed a second distance from the edge of the die.

Semiconductor wafer 120 undergoes electrical testing and inspection aspart of a quality control process. Manual visual inspection andautomated optical systems are used to perform inspections onsemiconductor wafer 120. Software can be used in the automated opticalanalysis of semiconductor wafer 120. Visual inspection methods mayemploy equipment such as a scanning electron microscope, high-intensityor ultra-violet light, or metallurgical microscope. Semiconductor wafer120 is inspected for structural characteristics including warpage,thickness variation, surface particulates, irregularities, cracks,delamination, and discoloration.

The active and passive components within semiconductor die 124 undergotesting at the wafer level for electrical performance and circuitfunction. Each semiconductor die 124 is tested for functionality andelectrical parameters, as shown in FIG. 3c , using a test probe head 136including a plurality of probes or test leads 138, or other testingdevice. Probes 138 are used to make electrical contact with nodes orcontact pads 132 on each semiconductor die 124 and provide electricalstimuli to the contact pads. Semiconductor die 124 responds to theelectrical stimuli, which is measured by computer test system 140 andcompared to an expected response to test functionality of thesemiconductor die. The electrical tests may include circuitfunctionality, lead integrity, resistivity, continuity, reliability,junction depth, ESD, RF performance, drive current, threshold current,leakage current, and operational parameters specific to the componenttype. The inspection and electrical testing of semiconductor wafer 120enables semiconductor die 124 that pass to be designated as known gooddie (KGD) for use in a semiconductor package.

In FIG. 3d , semiconductor wafer 120 is singulated through saw street126 using a saw blade or laser cutting tool 146 into individualsemiconductor die 124. The individual semiconductor die 124 can beinspected and electrically tested for identification of KGD postsingulation.

FIGS. 4a-4p illustrate, in relation to FIGS. 2 and 3 a-3 d, a soft maskmethod of forming a power MOSFET with a superjunction and surroundingLDD region on an active surface of semiconductor die 124. FIG. 4a showsa cross-sectional view of a portion of semiconductor die 124 used information of MOSFET cell 150. Typically, a plurality of MOSFET cells 150is formed on active surface 130, and connected in parallel, to create apower MOSFET device on semiconductor die 124. MOSFET cell 150 is used insemiconductor designs other than a discrete power MOSFET in otherembodiments.

MOSFET cell 150 can be an n-channel device (N-MOS) or a p-channel device(P-MOS), where “p” denotes a positive carrier type (holes) and “n”denotes a negative carrier type (electrons). Although the presentembodiment of MOSFET cell 150 is described in terms of an N-MOS deviceformed on semiconductor die 124 including P-doped base substratematerial 122, the opposite type semiconductor material can be used toform a P-MOS device.

In FIG. 4b , insulation or dielectric layer 152 is formed over activesurface 130 as a gate dielectric. Dielectric layer 152 contains one ormore layers of silicon dioxide (SiO2), silicon nitride (Si3N4), siliconoxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3),hafnium oxide (HfO2), polyimide (PI), benzocyclobutene (BCB),polybenzoxazoles (PBO), or other suitable dielectric material.Dielectric layer 152 is formed using PVD, CVD, screen printing, spincoating, spray coating, sintering, or thermal oxidation. In oneembodiment, a thin film of SiO2 is grown on active surface 130 bythermal oxidation.

In FIG. 4c , a polysilicon layer 154 is formed over dielectric layer152. Polysilicon layer 154 is used as the gate material in the finalstructure of MOSFET cell 150. In other embodiments, metal is used toform the gate of MOSFET cell 150. In some embodiments, polysilicon layer154 is doped with an N-type or P-type dopant. In FIG. 4d , photoresistlayer 156 is formed over polysilicon layer 154. A portion of photoresistlayer 156 is removed by an etching or photolithography process to exposea portion of polysilicon layer 154. A remaining portion of photoresistlayer 156 not removed in the etching process corresponds to a gatepattern of MOSFET cell 150.

In FIG. 4e , a portion of polysilicon layer 154 is removed by an etchingprocess using photoresist layer 156 as a mask. A remaining portion ofpolysilicon layer 154 serves as a polysilicon (poly) gate for MOSFETcell 150. Poly gate 154 will be electrically connected to a gateterminal of the final MOSFET device. Electric charge applied to polygate 154 will control the conductivity of a channel in base substratematerial 122 between subsequently formed source and drain regions.Because MOSFET cell 150 is an N-MOS device, a positive voltage appliedto poly gate 154 turns on the MOSFET cell. The positive voltage on polygate 154 will create an electric field through dielectric layer 152 toattract electrons, i.e., majority carriers, to an area in base substratematerial 122 under the poly gate, thereby creating a conduction channel.

In FIG. 4f , a remaining portion of photoresist layer 156 is removedafter the etching of polysilicon layer 154. Dielectric layer 152 remainsas a protective layer over MOSFET cell 150. In some embodiments,portions of dielectric layer 152 are removed. Dielectric layer 152between poly gate 154 and base substrate material 122 acts as a gatedielectric or gate oxide for MOSFET cell 150. Dielectric layer 152prevents direct electrical contact between poly gate 154 and basesubstrate material 122 while allowing an electric field from the polygate to penetrate the base substrate material to create a conductionchannel. FIG. 4g shows a 3 d perspective view of base substrate material122, dielectric layer 152, and poly gate 154. Poly gate 154 extendsacross MOSFET cell 150 over active surface 130. Poly gate 154 is formedas a uniform strip across MOSFET cell 150. Other shapes of poly gate 154are used in other embodiments. Dielectric layer 152 remains blanketedover active surface 130.

FIG. 4h illustrates photoresist layer 158 formed over dielectric layer152 and poly gate 154. A portion of photoresist layer 158 correspondingto a drain region of MOSFET cell 150 is removed using an etching orphotolithography process. A semiconductor doping process, e.g., ionimplantation, is used to deposit an N-type dopant, such as phosphorus,antimony, or arsenic, into base substrate material 122 to form LDDregion 160. Ion implantation is used to implant dopant material throughdielectric layer 152 by accounting for the thickness of the dielectriclayer when selecting the energy level of the ion implantation.

Photoresist layer 158 acts as a mask to form LDD region 160 in thedesired location for a drift region on active surface 130. In otherembodiments, LDD region 160 is self-aligned using poly gate 154. LDDregion 160 is a lightly doped region which conducts electricity from asubsequently formed drain contact region to an area under poly gate 154.LDD region 160 forms a PN junction, including a depletion region, atareas of contact with P-doped base substrate material 122. A remainingportion of photoresist layer 158 is removed after LDD region 160 isformed. LDD region 160 is formed extending across MOSFET cell 150 inparallel with poly gate 154, as shown in FIG. 4 p.

In FIG. 4i , photoresist layer 168 is formed over dielectric layer 152,poly gate 154, and LDD region 160. A portion of photoresist layer 168corresponding to a source region of MOSFET cell 150 is removed using anetching or photolithography process. A semiconductor doping process,e.g., ion implantation, is used to deposit a P-type dopant, such asboron, aluminum, or gallium, into base substrate material 122 to formP-channel region 170. P-channel region 170 is formed extending acrossMOSFET cell 150 in parallel with poly gate 154.

Photoresist layer 168 acts as a mask to form P-channel region 170 in theregion of base substrate material 122 desired as a source region, andlimits the amount of P-type dopant deposited into LDD region 160. Inother embodiments, P-channel region 170 is formed self-aligned with polygate 154. A thermal anneal process is performed on MOSFET cell 150 toextend P-channel region 170 laterally under poly gate 154. In someembodiments, P-channel region 170 contacts LDD region 160 under polygate 154.

P-channel region 170 is used to control the turn-on voltage of MOSFETcell 150. Due to P-channel region 170 being more heavily doped than basesubstrate material 122, more electrons will be required in a channelunder poly gate 154 to turn on MOSFET cell 150 as the P-channel regionextends further under the poly gate.

P-channel region 170 serves as a conduction path through MOSFET cell 150which is doped with a higher concentration than base substrate material122, reducing resistance for positive carriers, i.e., holes, whileMOSFET cell 150 is in avalanche or during commutation of the MOSFETcell. P-channel region 170 also slows the spread of the depletion regionbetween base substrate material 122 and LDD region 160 toward asubsequently formed source contact region as the depletion regionextends further into the base substrate material. P-channel region 170reduces the likelihood of the depletion region reaching the N+ dopedsource contact region. A remaining portion of photoresist layer 168 isremoved after P-channel region 170 is formed.

In FIG. 4j , photoresist layer 172 is formed over dielectric layer 152,poly gate 154, LDD region 160, and P-channel region 170. A portion ofphotoresist layer 172 corresponding to a P+ source contact region ofMOSFET cell 150 is removed using an etching or photolithography process.A semiconductor doping process, e.g., ion implantation, is used todeposit a P-type dopant, such as boron, aluminum, or gallium, intoP-channel region 170 to form P+ source contact region 174. P+ sourcecontact region 174 is formed extending across MOSFET cell 150 inparallel with poly gate 154, as shown in FIG. 4 p.

P+ source contact region 174 creates a heavily doped region withinP-channel region 170 to provide good ohmic contact between asubsequently formed metal source contact and base substrate material122. A remaining portion of photoresist layer 172 is removed afterformation of P+ source contact region 174.

FIG. 4k illustrates photoresist layer 176 formed over dielectric layer152, poly gate 154, LDD region 160, P-channel region 170, and P+ sourcecontact region 174. A portion of photoresist layer 176 corresponding toN+ source and drain contact regions is removed using an etching orphotolithography process. A semiconductor doping process, e.g., ionimplantation, is used to deposit an N-type dopant, such as arsenic,phosphorus, or antimony, into P-channel region 170 and LDD region 160 toform N+ source contact region 178 and N+ drain contact region 180. N+source contact region 178 and N+ drain contact region 180 are eachformed extending across MOSFET cell 150 in parallel with poly gate 154,as shown in FIG. 4p . In one embodiment, a first mask is used to form N+source contact region 178, and a second mask is used to form N+ draincontact region 180 in a separate deposition step.

N+ source contact region 178 serves as a first connection point forpower current through MOSFET cell 150 when the MOSFET cell is on. N+source contact region 178 creates a good ohmic connection with a metalsource contact subsequently formed over MOSFET cell 150. N+ draincontact region 180 serves as a second connection point for power currentthrough MOSFET cell 150 when the MOSFET cell is on. N+ drain contactregion 180 creates a good ohmic connection between LDD region 160 and ametal drain contact subsequently formed over MOSFET cell 150.

A metal source contact subsequently formed over MOSFET cell 150 isconnected to N+ source contact region 178 and P+ source contact region174. The metal source contact is connected to N+ source contact region178 as a conduction terminal through MOSFET cell 150 when the MOSFETcell is on. A positive charge applied to poly gate 154 attractselectrons to the area of base substrate material 122 under poly gate154. A channel of negative carriers is created connecting N+ sourcecontact region 178 and LDD region 160, which is negatively doped aswell, allowing current to flow from N+ drain contact region 180 to N+source contact region 178.

The metal source contact subsequently formed over MOSFET cell 150 isconnected to P+ source contact region 174 in order to control thevoltage of base substrate material 122. MOSFET cell 150 includes aparasitic NPN BJT transistor formed by N+ source contact region 178,P-doped base substrate material 122, and N-doped LDD region 160. Withouta connection between a metal source contact and base substrate material122 through P+ source contact region 174, the base substrate material,i.e., the base of the parasitic BJT, is electrically floating. Undercertain circumstances, the parasitic BJT activates and causes latch-upof MOSFET cell 150. Connecting the metal source contact to basesubstrate material 122 reduces the likelihood of latch-up, and creates adiode between P+ source contact region 174 and N+ drain contact region180 of MOSFET cell 150. When MOSFET cell 150 is off, current from thevoltage applied to N+ drain contact region 180 is limited by the diodeformed between the N+ drain contact region and P+ source contact region174. In some embodiments, a voltage greater than BVdss applied to N+drain contact region 180 puts the MOSFET cell into avalanche. WhenMOSFET cell 150 is in avalanche, the electric field in base substratematerial 122 is strong enough to generate pairs of holes and electrons.The generated holes flow out P+ source contact region 174, and thegenerated electrons flow out N+ drain contact region 180.

In FIG. 4l , photoresist layer 188 is formed over dielectric layer 152and poly gate 154. A portion of photoresist layer 188 corresponding to asuperjunction region is removed using an etching or photolithographyprocess. A semiconductor doping process, e.g., ion implantation, is usedto deposit an N-type dopant, such as arsenic, phosphorus, or antimony,into LDD region 160 to form N-drift region 190. A plurality of ionimplantation steps, or chain implants, is used to reach a desiredsuperjunction depth, Xj. Each subsequent implant is performed with avaried ion energy to inject dopant to a different depth between surface130 and a depth of Xj into base substrate material 122. In oneembodiment, two chain implants are performed per 0.50 μm of desireddepth into base substrate material 122.

In FIG. 4l , a first chain implant 190 a is performed which depositsN-type dopant to a depth of Xj. A second chain implant 190 b isperformed which deposits N-type dopant between chain implant 190 a andsurface 130. A thermal anneal performed after MOSFET cell 150 is formeddiffuses chain implants 190 a and 190 b into continuous and uniformvertical regions. In other embodiments, chain implants are not used anda single ion implantation is used to form N-drift region 190.

N-drift region 190 is formed as a band across MOSFET cell 150. N-driftregion 190 extends across MOSFET cell 150 in parallel with poly gate154. FIG. 4m illustrates a plan view of MOSFET cell 150 withoutdielectric layer 152, so N-drift region 190 is visible. Photoresistlayer 188 is formed over MOSFET cell 150, with a portion of thephotoresist layer removed to allow formation of N-drift region 190across MOSFET cell 150. N-drift region 190 is formed with a lengthcorresponding to the desired length, Lsj, of superjunction stripes forMOSFET cell 150 and a width which extends across the MOSFET cell. Aremaining portion of photoresist layer 188 is removed after N-driftregion 190 is formed.

In FIG. 4n , photoresist layer 198 is formed over dielectric layer 152and poly gate 154. A portion of photoresist layer 198 corresponding to aP-doped stripe area of a superjunction is removed using an etching orphotolithography process. A semiconductor doping process, e.g., ionimplantation, is used to deposit a P-type dopant, such as boron,aluminum, or gallium, into N-drift region 190 to form P-doped stripes200. P-doped stripes 200 are formed to approximately the same depth, Xj,as N-drift region 190. In embodiments where chain implants are used toincrease the depth of N-drift region 190, similar chain implants withsimilar ion energies are used to align the depth of P-doped stripes 200to the depth of the N-drift region.

FIG. 4n illustrates a first chain implant 200 a which deposits P-typedopant to a depth of Xj. A second chain implant 200 b is performed whichdeposits P-type dopant between chain implant 200 a and surface 130. Athermal anneal performed after MOSFET cell 150 is formed diffuses chainimplants 200 a and 200 b into continuous and uniform vertical regions.

FIG. 4o illustrates a plan view of MOSFET cell 150 without dielectriclayer 152, so that P-doped stripes 200 are visible. Photoresist layer198 is formed over MOSFET cell 150, with a portion of the photoresistlayer removed to allow formation of P-doped stripes 200 in N-driftregion 190. Photoresist layer 198 forms a mask, such that P-dopedstripes 200 are formed with a length approximately equal to the N-driftregion 190, Lsj. Each P-doped stripe 200 is formed with approximatelythe same depth into base substrate material 122, Xj, as N-drift region190. Each individual P-doped stripe 200 is formed with a width, Wp, asdetermined by the design parameters of the superjunction. Eachindividual P-doped stripe 200 is spaced apart from an adjacent P-dopedstripe by a distance of Wn, as determined by the design parameters ofthe superjunction. The area between adjacent P-doped stripes 200 remainscovered by photoresist layer 198 so that portions of N-drift region 190remain N-doped. The mask pattern of photoresist 198 over N-drift region190 protects portions of the N-drift region from being doped along withP-doped stripes 200.

Wn is the desired width of N-doped stripes of the superjunction. Leavingphotoresist layer 198 as a mask between adjacent P-doped stripes 200causes the deposition of P-type dopant to form the P-doped stripes whileleaving portions of N-drift region 190 as stripes having a negativedoping. Enough P-type dopant is deposited in P-doped stripes 200 tocounteract the preexisting N-type doping, as well as reach the desiredlevel of P-type doping in the P-doped stripes. The remaining N-dopedstripes 190 are interleaved with P-doped stripes 200.

The described process of forming P-doped stripes 200 on a field ofN-doped material self-aligns the P-doped stripes to N-doped stripes 190.An edge of each P-doped stripe 200 contacts an edge of adjacent N-dopedstripes 190 to create the necessary PN junction and depletion regionbetween each P-doped stripe and N-doped stripe. No excess space existsin base substrate material 122 between N-doped stripes 190 and P-dopedstripes 200 because the P-doped stripes are formed self-aligned to acommon boundary with the N-doped stripes.

In one embodiment, Wn and Wp are approximately equal. In the case whereWn and Wp, i.e., the widths of N-doped stripes 190 and P-doped stripes200, are approximately equal, the doping concentrations of the stripesare also made approximately equal. With equal widths and equal dopingconcentrations, a depletion region between an N-doped stripe 190 andadjacent P-doped stripe 200 grows into the N-doped and P-doped stripe atapproximately the same rate. N-doped stripes 190 are fully depleted atapproximately the same voltage at which P-doped stripes 200 are fullydepleted, which improves the benefit of the superjunction to BVdss. Inother embodiments, the width of N-doped stripes 190, Wn, and the widthof P-doped stripes 200, Wp, are different values. When Wn is greaterthan Wp, the doping concentration of N-doped stripes 190 is made lowerthan the doping concentration of P-doped stripes 200 in order tomaintain proper charge balancing between the P-doped stripes and N-dopedstripes. When Wn is less than Wp, the doping concentration of N-dopedstripes 190 is made greater than the doping concentration of P-dopedstripes 200 to maintain proper charge balancing. When N-doped stripes190 are properly charge balanced with P-doped stripes 200, the N-dopedstripes are fully depleted at the same voltage at which the P-dopedstripes are fully depleted, even with different widths Wn and Wp. Chargebalancing occurs when the product of the doping concentration of N-dopedstripes 190 and the width of the N-doped stripes, Wn, is equal to theproduct of the doping concentration of P-doped stripes 200 and the widthof the P-doped stripes, Wp. The depth of stripes 190 and 200, Xj, is notfactored into the charge balancing of a superjunction if the depth ofeach stripe is equal.

FIG. 4p illustrates MOSFET cell 150 with photoresist layer 198 removed.Dielectric layer 152 is illustrated as being partially removed to betterillustrate the doping areas of active surface 130. When a positivecharge is exhibited on poly gate 154, negative carriers, i.e.,electrons, are attracted to the area of P-channel region 170 and basesubstrate material 122 under the poly gate. When the positive charge onpoly gate 154 is of a high enough magnitude, electrons attracted underthe poly gate electrically connect N+ source contact region 178 and LDDregion 160. Due to the conduction path of electrons under poly gate 154,a path of negative carriers is continuous from N+ drain contact region180, through LDD region 160 and N-doped stripes 190, and to N+ sourcecontact region 178. LDD region 160 electrically connects the channelformed under poly gate 154 to one end of N-doped stripes 190. LDD region160 also electrically connects a second end of N-doped stripes 190 to N+drain contact region 180.

Current through P-doped stripes 200 when MOSFET cell 150 is on islimited because of a depletion region formed between the P-doped stripesand N-doped stripes 190. However, RDSON of MOSFET cell 150 is reducedcompared to a drift region using only LDD region 160 due to the higherdoping concentration of stripes 190 compared to the LDD region. WhenMOSFET cell 150 is on, current flows from a power signal connected to N+drain contact region 180, through the portion of LDD region 160 adjacentto the N+ drain contact region, and through the N-doped stripes. Currentcontinues through the portion of LDD region 160 between N-doped stripes190 and poly gate 154, then through a conductive channel formed underpoly gate 154 to N+ source contact region 178. The electronic circuit tobe switched is connected to N+ source contact region 178 to receive thepower signal. In other configurations, N+ source contact region 178 isconnected to a ground potential, while the circuit to be switched isconnected in series between N+ drain contact region 180 and a powersource.

When MOSFET cell 150 is off, i.e., insufficient positive charge existson poly gate 154 to form a conduction channel under the poly gate, N+source contact region 178 and LDD region 160 are not electricallyconnected. The power signal at N+ drain contact region 180 does not flowthrough MOSFET cell 150 to N+ source contact region 178. The PNjunctions between N-doped stripes 190, P-doped stripes 200, LDD region160, and base substrate material 122 create a diode with N+ draincontact region 180 as the cathode and P+ source contact region 174 asthe anode. The identified diode limits current from N+ drain contactregion 180 to P+ source contact region 174 until the voltage on the N+drain contact region reaches the breakdown voltage of the diode.

N-doped stripes 190 form superjunction 202 with P-doped stripes 200.Superjunction 202 is surrounded by LDD region 160. LDD region 160 existsbelow and at the ends of each N-doped stripe 190 and P-doped stripe 200.Together, superjunction 202 and LDD region 160 form a drift region ofMOSFET cell 150. The superjunction formed by stripes 190 and 200provides a low resistance conduction path between drain contact region180 and gate 154. LDD region 160 provides a buffer area betweensuperjunction 202 and N+ drain contact region 180, as well as betweenthe superjunction and the area under poly gate 154.

Due to the increased doping concentrations of stripes 190 and 200, anincreased electric field exists at the depletion region between adjacentstripes compared to the depletion region between LDD region 160 and basesubstrate material 122 when superjunction 202 is not used. LDD region160 acts as a buffer area between the higher electric fields ofdepletion regions of superjunction 202 and electric field peaks at N+drain contact region 180 and under poly gate 154. Limiting the electricfield at N+ drain contact region 180 and under poly gate 154 increasesBVdss and reduces the likelihood of hot carriers being injected intodielectric layer 152.

Accordingly, stripes 190 and 200 are formed such that some distance isprovided between the stripes and N+ drain contact region 180 to bufferthe N+ drain contact region from increased electric fields. A distanceis also provided between poly gate 154 and stripes 190 and 200 to bufferthe poly gate from increased electric fields.

LDD region 160 is provided to complete a conduction path between N+drain contact region 180 and N-doped stripes 190. Without LDD region160, N+ drain contact region 180 is surrounded by P-doped base substrate122. A depletion region forms surrounding N+ drain contact region 180,reducing current flow through MOSFET cell 150. LDD region 160 provides anegatively doped region between N+ drain contact region 180 and N-dopedstripes 190 for proper conduction through the drift region when MOSFETcell 150 is on.

LDD region 160 also completes a conduction path between N-doped stripes190 and the area under poly gate 154. A positive charge on poly gate 154attracts electrons to the area under the poly gate, creating aconductive channel connecting N+ source contact region 178 and LDDregion 160. The conduction channel under poly gate 154 does not easilyreach N-doped stripes 190 as required for conduction through MOSFET cell150. LDD region 160 of MOSFET cell 150 bridges the gap between N-dopedstripes 190 and poly gate 154.

LDD region 160 provides a buffer area between N+ drain contact region180 and the increased electric field of stripes 190 and 200. LDD region160 also provides a buffer area between poly gate 154 and the increasedelectric field of stripes 190 and 200. LDD region 160 is doped withnegative carriers, and operates as short segments of the drift regionformed by the LDD region and superjunction 202. Together, LDD region160, N-doped stripes 190, and P-doped stripes 200 form a drift region ofMOSFET cell 150 connecting N+ drain contact region 180 to the area underpoly gate 154. N-doped stripes 190 and P-doped stripes 200 formsuperjunction 202 which provides a low resistance conduction path, whilealso supporting a high BVdss. LDD region 160 provides a buffer area toprevent higher electric fields of superjunction 202 from combining withelectric field peaks at the area under poly gate 154 or N+ drain contactregion 180.

While the doped regions in base substrate material 122 are illustratedas being formed in one order, the various regions are doped in adifferent order of steps in other embodiments.

FIGS. 5a-5h show, in relation to FIGS. 4a-4p , a hard mask method offorming power MOSFET cell 210 with a superjunction and surrounding LDDregion. Typically, a plurality of MOSFET cells 210 is formed on activesurface 130, and connected in parallel, to create a power MOSFET device.MOSFET cell 210 is used in semiconductor designs other than a discretepower MOSFET in other embodiments.

Continuing from FIG. 4k , FIG. 5a illustrates photoresist layer 218formed over dielectric layer 152 and poly gate 154. A portion ofphotoresist layer 218 corresponding to a superjunction region is removedusing an etching or photolithography process. A semiconductor dopingprocess, e.g., ion implantation, is used to deposit an N-type dopant,such as arsenic, phosphorus, or antimony, into LDD region 160 to formN-drift region 220. In some embodiments, a plurality of ion implantationsteps, or chain implants, is used to reach a desired superjunctiondepth, Xj. Each subsequent implant is performed with a varied ion energyto inject dopant to a different depth between surface 130 and a depth ofXj into base substrate material 122. In one embodiment, two chainimplants are performed per 0.50 μm of desired depth into base substratematerial 122.

In FIG. 5a , three ion implants are used to form N-drift region 220instead of two ion implants as with N-drift region 190 in FIG. 4l . Afirst chain implant 220 a is performed which deposits N-type dopant to adepth of Xj. A second chain implant 220 b is performed which depositsN-type dopant over implant 220 a and extending partially to surface 130.A third chain implant 220 c is performed which deposits N-type dopantbetween chain implant 220 b and surface 130. A thermal anneal performedafter MOSFET cell 210 is formed diffuses ion implants 220 a, 220 b, and220 c into a vertically continuous and uniform region.

N-drift region 220 is formed as a band across MOSFET cell 210. N-driftregion 220 extends across MOSFET cell 210 in parallel with poly gate154. N-drift region 220 is formed deeper into base substrate material122 than N-drift region 190 in FIG. 4l . A hard mask used to form theP-doped stripes of a superjunction in N-drift region 220 allows for ahigher energy ion implantation which reaches an increased depth withinbase substrate material 122. Because the hard mask allows P-dopedstripes to be formed to a greater depth, i.e., higher Xj, N-drift region220 are formed to a greater depth as well.

FIG. 5b illustrates a plan view of MOSFET cell 210 without dielectriclayer 152, so N-drift region 220 is visible. Photoresist layer 218 isformed over MOSFET cell 210 with a portion of the photoresist layerremoved to allow formation of N-drift region 220 across MOSFET cell 210.N-drift region 220 is formed with a length corresponding to the desiredlength, Lsj, of superjunction stripes for MOSFET cell 210 and a widthwhich extends across the MOSFET cell. A remaining portion of photoresistlayer 218 is removed after N-drift region 220 is formed.

In FIG. 5c , hard mask 226 is deposited over active surface 130,dielectric layer 152, and poly gate 154. Hard mask 226 is formed from ahard mask material, e.g., SiO2. In one embodiment, a thickness of hardmask 226 is adjusted according to the desired implant depth, Xj. Asurface of hard mask 226 opposite active surface 130 undergoes aplanarization process such as chemical-mechanical planarization (CMP).Photoresist layer 228 is formed over hard mask 226.

FIG. 5d illustrates removing a portion of photoresist layer 228 and hardmask 226 corresponding to a desired location for subsequently formedP-doped stripes of a superjunction. First, a portion of photoresistlayer 228 is removed by an etching or photolithography process in thedesired superjunction pattern. Next, a portion of hard mask 226 isremoved by an etching process using photoresist layer 228 as a mask,thereby creating a similar pattern in hard mask 226 as was formed inphotoresist layer 228.

A semiconductor doping process, e.g., ion implantation, is used todeposit a P-type dopant, such as boron, aluminum, or gallium, intoN-drift region 220 to form P-doped stripes 230. P-doped stripes 230 areformed to approximately the same depth, Xj, as N-drift region 220. Inembodiments where chain implants are used to increase the depth ofN-drift region 220, similar chain implants with similar ion energies areused to align the depth of P-doped stripes 230 to the depth of theN-drift region.

P-doped stripes 230 are formed using hard mask 226 as a mask instead ofphotoresist layer 198 as with P-doped stripes 200 in FIG. 4n . Hard mask226 allows for a higher resolution pattern to be formed due to theability of the hard mask to withstand higher energy ion implantation.Higher resolution patterning allows thinner N-doped stripes 220 andP-doped stripes 230, i.e., lower Wn and Wp. Lower widths Wn and Wp allowfor a higher doping concentration of the superjunction of power MOSFETcell 210 while N-doped stripes 220 and P-doped stripes 230 still fullydeplete prior to breakdown of MOSFET cell 210. A higher dopingconcentration of N-doped stripes 220 and P-doped stripes 230 reducesRDSON of MOSFET cell 210. Therefore, using hard mask 226 instead ofphotoresist layer 198 in FIG. 4n allows for a deeper superjunction andlower stripe widths, reducing RDSON. Conduction losses of MOSFET cell210 are reduced by the reduction of RDSON.

FIG. 5e illustrates a plan view of MOSFET cell 210 without dielectriclayer 152, so that P-doped stripes 230 are visible. Hard mask 226 andphotoresist layer 228 are formed over MOSFET cell 210, with portions ofthe photoresist layer and hard mask removed for formation of P-dopedstripes 230 in N-drift region 220. Photoresist layer 228 forms a mask toetch hard mask 226. Hard mask 226 is etched to form a mask used forformation of P-doped stripes 230. P-doped stripes 230 are formed with alength approximately equal to the N-drift region 220, i.e., Lsj. EachP-doped stripe 230 is formed with approximately the same depth into basesubstrate material 122, i.e., Xj, as N-drift region 220. Each individualP-doped stripe 230 is formed with a width, Wp, as determined by thedesign parameters of the superjunction. Each individual P-doped stripe230 is separated from an adjacent P-doped stripe by a distance of Wn, asdetermined by the design parameters of the superjunction. The areabetween adjacent P-doped stripes 230 remains covered by hard mask 226 sothat portions of N-drift region 220 are not doped along with the P-dopedstripes. The use of hard mask 226 allows for a lower Wn and Wp to beused.

Wn is the desired width of N-doped stripes of the superjunction. Leavinghard mask 226 as a mask between adjacent P-doped stripes 230 causes thedeposition of P-type dopant to form the P-doped stripes while leavingportions of N-drift region 220 as stripes having a negative doping.Enough P-type dopant is deposited in P-doped stripes 230 to counteractthe preexisting N-type doping, as well as reach the desired level ofP-type doping in the P-doped stripes. The remaining N-doped stripes 220are interleaved with P-doped stripes 230.

The described process of forming P-doped stripes 230 on a field ofN-doped material self-aligns the P-doped stripes to N-doped stripes 220.An edge of each P-doped stripe 230 contacts an edge of adjacent N-dopedstripes 220 to properly create the necessary PN junction and depletionregion between each P-doped stripe and N-doped stripe. No excess spaceexists in base substrate material 122 between N-doped stripes 220 andP-doped stripes 230 because the P-doped stripes are formed self-alignedto a common boundary with the N-doped stripes.

In one embodiment, Wn and Wp are approximately equal. In the case whereWn and Wp, i.e., the widths of N-doped stripes 220 and P-doped stripes230, are approximately equal, the doping concentrations of the stripesare also made approximately equal. With equal widths and equal dopingconcentrations, a depletion region between an N-doped stripe 220 andadjacent P-doped stripe 230 grows into the N-doped stripe and P-dopedstripe at approximately the same rate. N-doped stripes 220 are fullydepleted at approximately the same voltage level as P-doped stripes 230,which improves performance of the superjunction. In other embodiments,the width of N-doped stripes 220, Wn, and the width of P-doped stripes230, Wp, are selected to be different values. When Wn is greater thanWp, the doping concentration of N-doped stripes 220 is made lower thanthe doping concentration of P-doped stripes 230 in order to maintainproper charge balancing between the P-doped stripes and N-doped stripes.When Wn is less than Wp, the doping concentration of N-doped stripes 220is made greater than the doping concentration of P-doped stripes 230 tomaintain proper charge balancing. When N-doped stripes 220 are properlycharge balanced with P-doped stripes 230, the N-doped stripes are fullydepleted at the same voltage as the P-doped stripes, even with differentstripe widths.

FIG. 5f illustrates MOSFET cell 210 with photoresist layer 228 and hardmask 226 removed. Dielectric layer 152 is illustrated as being partiallyremoved to better illustrate the doping areas of active surface 130.N-doped stripes 220 and P-doped stripes 230 are doped at a higherconcentration, formed with lower widths Wn and Wp, and include a deeperjunction depth Xj than MOSFET cell 150 in FIG. 4p to give MOSFET cell210 a lower RDSON. Other than the formation of P-doped stripes 230 usinga hard mask instead of a soft mask, MOSFET cell 210 is formed andoperates similarly to MOSFET cell 150. Hard mask 226 withstands a higherenergy of ion implantation as compared to a soft mask. Higher energy ionimplantation enables a higher resolution of stripes to be formed forsuperjunction 232 compared with superjunction 202, lowering Wn and Wp.Lowering Wn and Wp allows the doping concentrations of N-doped stripes220 and P-doped stripes 230 to be increased because the stripes willstill fully deplete before breakdown voltage of MOSFET cell 210 isreached. Higher energy ion implantation also allows a deeperimplantation into base substrate material 122, thereby increasing Xj andreducing RDSON. Using hard mask 226 allows RDSON to be reduced byincreasing junction depth, Xj, and reducing stripe width, Wn and Wp, ofsuperjunction 232.

FIG. 5f illustrates the ideal case where the ends of N-doped stripes 220and P-doped stripes 230 are aligned along line 236. One difficulty ofmanufacturing superjunction 202 of MOSFET cell 150 and superjunction 232of MOSFET cell 210 is achieving proper alignment of the ends of theP-doped stripes with the ends of the N-doped stripes. The stripes ofsuperjunctions 202 and 232 are self-aligned to each other by forming theP-doped stripes on a field of N-doped material. However, the ends ofstripes 220 and 230 are not self-aligned. Aligning the ends of theN-doped stripes and P-doped stripes of a superjunction is important forcharge balancing of the superjunction and improving characteristics of aMOSFET cell. Misalignment of N-doped stripes and P-doped stripes at thesource end of the superjunction reduces BVdss. Due to alignmenttolerances of the manufacturing equipment and processes used to formMOSFETs 150 and 210, it is difficult to achieve proper alignment of theends of the P-doped stripes and N-doped stripes.

FIG. 5g illustrates one possible misalignment case. The edges of P-dopedstripes 230 toward poly gate 154 are formed shorter than N-drift region220, and are located within the N-drift region. When the source ends ofP-doped stripes 230 are formed further away from poly gate 154 than thesource end of N-drift region 220, BVdss is reduced. The variation inalignment of N-drift region 220 and P-doped stripes 230 is kept withinthe width of the stripes, Wn and Wp, to provide sufficient chargebalancing. A larger value for Wn and Wp is used to ensure themisalignment between the ends of stripes 220 and 230 is less than Wn andWp. Requiring a larger Wn and Wp limits the doping concentration used inN-doped stripes 220 and P-doped stripes 230, which raises RDSON ofMOSFET cell 210.

FIG. 5h illustrates a second possible misalignment case, with the edgeof P-doped stripes 230 extending outside of N-drift region 230 towardpoly gate 154. When the source ends of P-doped stripes 230 are formedcloser to poly gate 154 than the source end of N-doped stripes 220,RDSON of MOSFET cell 210 is increased. Some of the conduction area ofLDD region 160 is replaced by P-doped stripes 230 which conduct lesscurrent than the LDD region when MOSFET cell 210 is on. Reducing theconduction area of LDD region 160 adds resistance to the LDD region,increasing RDSON.

FIGS. 6a-6k illustrate, in relation to FIGS. 5a-5h , a hard mask methodof forming MOSFET cell 250 with N-doped stripes and P-doped stripesincluding self-aligned lengths. Typically, a plurality of MOSFET cells250 is formed on active surface 130, and connected in parallel, tocreate a power MOSFET device. MOSFET cell 250 is used in semiconductordesigns other than a discrete power MOSFET in other embodiments.

Continuing from FIG. 4k , FIG. 6a illustrates hard mask 252, etch stoplayer 254, and photoresist layer 256 formed over active surface 130,dielectric layer 152, and poly gate 154. Hard mask 252 is formed fromSiO2 or another hard mask material. Etch stop layer 254 is formed fromnitride, polysilicon, or another material with high etch selectivitywith respect to hard mask 252.

FIG. 6b illustrates opening 258 formed in hard mask 252, etch stop layer254, and photoresist layer 256. First, a portion of photoresist layer256 corresponding to a superjunction area for MOSFET cell 250 is removedusing an etching or photolithography process. Next, etch stop layer 254and hard mask 252 are etched using photoresist layer 256 as a mask.

In FIG. 6c , a remaining portion of photoresist layer 256 is removed. Asemiconductor doping process, e.g., ion implantation, is used to depositan N-type dopant, such as arsenic, phosphorus, or antimony, into LDDregion 160 to form N-drift region 260. In some embodiments, a pluralityof ion implantation steps, or chain implants, is used to reach a desiredsuperjunction depth, Xj. Each subsequent implant is performed with avaried ion energy to inject dopant to a different depth between surface130 and a desired junction depth, Xj, into base substrate material 122.In one embodiment, two chain implants are performed per 0.50 μm ofdesired depth into base substrate material 122.

N-drift region 260 is formed as a band across MOSFET cell 250 using hardmask 252. N-drift region 260 extends across MOSFET cell 250 in parallelwith poly gate 154. FIG. 6d illustrates a 3D perspective view of MOSFETcell 250 with opening 258, and with dielectric layer 152 partiallyremoved to better illustrate N-drift region 260. Opening 258 is formedover MOSFET cell 250 to allow formation of N-drift region 260 across theMOSFET cell. N-drift region 260 is formed on active surface 130 throughopening 258 with a length corresponding to the desired length, Lsj, ofsuperjunction stripes for MOSFET cell 250 and a width extending acrossthe MOSFET cell. N-drift region 260 is formed with an end or edge 261toward poly gate 154 and an end or edge 263 toward N+ drain contactregion 180.

FIG. 6e illustrates hard mask 264 and photoresist layer 266 formed overhard mask 252, etch stop layer 254, and dielectric layer 152. Hard mask264 is formed from SiO2 or another hard mask material. A CMP or otherplanarization process is performed on hard mask 264 prior to formingphotoresist layer 266.

FIG. 6f illustrates opening 268 formed in hard mask 264 and photoresistlayer 266. First, a portion of photoresist layer 266 is removedcorresponding to a desired pattern for subsequently formed P-dopedstripes of a superjunction. Next, a portion of hard mask 264 is removedusing photoresist layer 266 as a mask. Opening 268 in hard mask 264 andphotoresist layer 266 extends lengthwise beyond the opening formed inhard mask 252 and etch stop layer 254. That is, the length of opening268 is longer than the desired length of the superjunction, Lsj. Etchstop layer 254 protects hard mask 252 during the etching of hard mask264. Opening 268 in hard mask 264 extends lengthwise past ends 261 and263 of N-drift region 260.

In FIG. 6g , a remaining portion of photoresist layer 266 is removed. Asemiconductor doping process, e.g., ion implantation, is used to deposita P-type dopant, such as boron, aluminum, or gallium, into N-driftregion 260 to form P-doped stripes 270. P-doped stripes 270 are formedto approximately the same depth, Xj, as N-drift region 260. Inembodiments where chain implants are used to increase the depth ofN-drift region 260, similar chain implants with similar ion energies areused to align the depth of P-doped stripes 270 to the depth of theN-drift region. Hard mask 264 and hard mask 252 are used as masks in theformation of P-doped stripes 270. Hard mask 252 controls the length ofP-doped stripes 270, while hard mask 264 controls the width of P-dopedstripes 270 and the width of portions of N-drift region 260 which remainas N-doped stripes. A portion of hard mask 252 and a portion of hardmask 264 are used to form P-doped stripes 270.

FIG. 6h illustrates a plan view of openings 268 formed over MOSFET cell250. Dielectric layer 152 is not shown, in order to better illustratethe doping areas of MOSFET cell 250. Openings 268 extend over the edgesof etch stop layer 254 and hard mask 252 such that portions of etch stoplayer 254 are visible in openings 268. During formation of P-dopedstripes 270, hard mask 264 defines the width of the P-doped stripes, Wp,and N-doped stripes 260, Wn. Hard mask 264 self-aligns P-doped stripes270 to N-doped stripes 260 in the X direction, such that each P-dopedstripe includes a common edge with two adjacent N-doped stripes, becausethe P-doped stripes are formed in a field of N-doped material. Hard mask252 and etch stop layer 254 self-align the ends of P-doped stripes 270with ends 261 and 263 of N-doped stripes 260 because hard mask 252 isused to form the ends of the P-doped stripes and N-doped stripes. Hardmask 264 is etched beyond hard mask 252 and etch stop layer 254lengthwise, i.e., in the Y direction, beyond edges 261 and 263 so thathard mask 252 and etch stop layer 254 are used to define the length ofP-doped stripes 270. The ends of P-doped stripes 270 and N-doped stripes260 are self-aligned along lines 261 and 263 because hard mask 252defines the length of the P-doped stripes and N-doped stripes. Hard mask264 self-aligns N-doped stripes 260 and P-doped stripes 270 in the Xdirection, while hard mask 252 and etch stop layer 254 self-align theN-doped stripes and P-doped stripes in the Y direction.

FIG. 6i illustrates MOSFET cell 250 with hard mask 252, etch stop layer254, and hard mask 264 removed. Dielectric layer 152 is illustrated asbeing partially removed to better illustrate the doping areas of activesurface 130. The hard mask process of forming P-doped stripes 270 allowsthe P-doped stripes and N-doped stripes 260 to be doped at a higherconcentration and with lower widths Wn and Wp, as well as with a deeperjunction depth Xj, compared with using the soft mask process illustratedin FIGS. 4a-4p . Using a hard mask process to form N-doped stripes 260and P-doped stripes 270 allows the ends of the stripes to beself-aligned to lines 261 and 263. Self-aligning the ends of N-dopedstripes 260 and P-doped stripes 270 at lines 261 and 263 improves thecharge balancing of superjunction 272. A properly charge balancedsuperjunction 272 increases the benefit of the superjunction on theRDSON and BVdss of MOSFET cell 250. Other than forming N-doped stripes260 and P-doped stripes 270 with self-aligned ends using a hard mask,MOSFET cell 250 is formed and operates similarly to MOSFET cells 150 and210.

FIG. 6j illustrates a plan view of MOSFET cell 250 without dielectriclayer 152, showing the doping regions formed in base substrate material122. N+ drain contact region 180 is connected to a drain terminal of aMOSFET device which includes MOSFET cell 250. N+ source contact region178 and P+ source contact region 174 are connected to a source terminalof the MOSFET device. Poly gate 154 is connected to a gate terminal ofthe MOSFET device. When MOSFET cell 250 is turned on, electric currentflows from N+ drain contact region 180 to N+ source contact region 178via the drift region formed by N-doped stripes 260, P-doped stripes 270,and LDD region 160. Current flows through the drift region, then througha channel of electrons formed under poly gate 154, to N+ source contactregion 178. P+ source contact region 174 is used to bias the parasiticBJT of MOSFET cell 250 to prevent latch-up. P+ source contact region 174also allows current through MOSFET cell 250 when the MOSFET cell is inavalanche. P-doped stripes 270 and N-doped stripes 260 are self-alignedat lines 261 and 263 by using hard mask 252 to define the lengths ofeach stripe.

FIG. 6k illustrates a cross-sectional view of a portion of MOSFET cell250. N-doped stripes 260 and P-doped stripes 270 are interleaved acrossMOSFET cell 250. In the illustrated embodiment, the width of N-dopedstripes 260, Wn, and the width of P-doped stripes 270, Wp, are equal. Inother embodiments, Wn is made a different value than Wp. Each N-dopedstripe 260 and P-doped stripe 270 includes an approximately uniformdepth, Xj. A portion of LDD region 160 remains under N-doped stripes 260and P-doped stripes 270. A portion of base substrate material 122 whichwas not doped during the formation of MOSFET cell 250 remains under LDDregion 160.

The self-aligned hard mask process for forming superjunction 272illustrated in FIGS. 6a-6k is used to form other types of devices thanpower MOSFET cells in other embodiments. In one embodiment, a diode isformed using a superjunction self-aligned by the process disclosed inFIGS. 6a-6k . In other embodiments, a vertical MOSFET is formed using asuperjunction self-aligned by the process disclosed in FIGS. 6a -6 k.

FIG. 7 illustrates MOSFET cell 280. Although MOSFET cell 280 is formedusing the self-aligned hard mask process of FIGS. 6a-6k , the MOSFETcell is formed using the soft mask process illustrated in FIGS. 4a-4p orthe hard mask process illustrated in FIGS. 5a-5f in other embodiments.MOSFET cell 280 includes N-drift region 290 which extends beyond thesuperjunction length, Lsj, and P-doped stripes 270, to N+ drain contactregion 180. N-drift region 290 is formed with a longer mask opening thanP-doped stripes 270 so that only the ends of the N-drift region andP-doped stripes toward poly gate 154 are aligned. When formed using theself-aligning process illustrated in FIGS. 6a-6k , hard mask 252 isetched over N+ drain contact region 180, while hard mask 264 is etchedto line 263, so stripes 260 and 270 are self-aligned at line 261 but notline 263. Hard mask 252 defines the endpoint of P-doped stripes 270 atline 261, while hard mask 264 defines the endpoint of P-doped stripes270 at line 263. P-doped stripes 270 are formed with ends 291 toward N+drain contact region 180 which are surrounded by N-doped drift region290. N+ drain contact region 180 is surrounded by N-doped drift region290.

Extending N-drift region 290 to N+ drain contact region 180 benefitsRDSON of MOSFET cell 280. N-drift region 290 includes a higher dopingconcentration than LDD region 160, and reduces the resistance forcurrent flowing between N+ drain contact region 180 and thesuperjunction formed by the N-drift region and P-doped stripes 270.N-drift region 290 also operates as an adaptive RESURF or drain bufferzone around N+ drain contact region 180.

FIG. 8 illustrates MOSFET cell 300. Although MOSFET cell 300 is formedusing the self-aligned hard mask process of FIGS. 6a-6k , the MOSFETcell is formed using the soft mask process illustrated in FIGS. 4a-4p orthe hard mask process illustrated in FIGS. 5a-5f in other embodiments.MOSFET cell 300 includes source trench 301. During formation of MOSFETcell 300, source trench 301 is etched into P-channel region 170 of basesubstrate material 122 prior to the formation of P+ source contactregion 302. Source trench 301 extends across MOSFET cell 300 in parallelwith poly gate 154. P+ source contact region 302 and N+ source contactregion 304 are formed using a mask similarly to P+ source contact region174 and N+ source contact region 178 in FIGS. 4j-4k . However, due tosource trench 301, P+ source contact region 302 is formed further awayfrom active surface 130 than N+ source contact region 304. With P+source contact region 302 below the level of N+ source contact region304, the width of the N+ source contact region can be extended over theP+ source contact region.

Using a wider N+ source contact region 304 decreases RDSON of MOSFETcell 300 by including a larger heavily doped area to reduce resistance.In addition, source trench 301 improves the ability of metal sourcecontacts subsequently formed in the source trench to make goodelectrical contact with P+ source contact region 302 and N+ sourcecontact region 304. In one embodiment, tungsten contacts are formedperiodically spaced in source trench 301, each electrically connected toP+ source contact region 302 and N+ source contact region 304. Inanother embodiment, source trench 301 is filled with tungsten or anothermetal to form a contact bar across MOSFET cell 300 electricallyconnected to P+ source contact region 302 and N+ source contact region304. In addition, the area of P+ source contact region 302 can beincreased without taking away from the area of N+ source contact region304.

FIG. 9 illustrates MOSFET cell 310. Although MOSFET cell 310 is formedusing the self-aligned hard mask process of FIGS. 6a-6k , the MOSFETcell is formed using the soft mask process illustrated in FIGS. 4a-4p orthe hard mask process illustrated in FIGS. 5a-5f in other embodiments.After formation of N-doped stripes 260 and P-doped stripes 270, sourcefield plate 312 and drain field plate 314 are formed over LDD region 160and the stripes. Source field plate 312 is formed over additionaldielectric or insulating layer 316, and drain field plate 314 is formedover additional dielectric or insulating layer 318. In otherembodiments, dielectric layers 316 and 318 are formed as a continuousdielectric layer under source field plate 312 and drain field plate 314.Dielectric layers 316 and 318 contain one or more layers of SiO2, Si3N4,SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectricmaterial having similar structural and insulating properties. Sourcefield plate 312 is electrically connected to metal source contact 320,which is further electrically connected to N+ source contact region 178,P+ source contact region 174, and a source terminal of a MOSFET devicewhich includes MOSFET cell 310. Drain field plate 314 is electricallyconnected to metal drain contact 322, which is further electricallyconnected to N+ drain contact region 180 and a drain terminal of aMOSFET device which includes MOSFET cell 310. Metal source contact 320and metal drain contact 322 are formed in openings of dielectric layer152.

MOSFET cell 310 includes points of fixed potential under poly gate 154and at N+ drain contact region 180. The points of fixed potential causeelectric field peaks under poly gate 154 and at N+ drain contact region180, reducing BVdss. Field plates 312 and 314 modify the electric fieldin LDD region 160, N-doped stripes 260, and P-doped stripes 270. Fieldplates 312 and 314 effectively move the points of fixed potential, andtherefore the electric field peaks, away from poly gate 154 and N+ draincontact region 180. By moving the electric field peaks away from polygate 154 and N+ drain contact region 180, the electric field at the polygate and N+ drain contact region are reduced. BVdss of MOSFET cell 310is improved, and a risk of hot carrier injection is reduced.

The above illustrated MOSFET cells, e.g., MOSFET cell 150 in FIG. 4p ,MOSFET cell 210 in FIG. 5f , MOSFET cell 250 in FIG. 6i , MOSFET cell300 in FIG. 8, and MOSFET cell 310 in FIG. 9, show LDD region 160extending from a gate end of a superjunction to a drain end of thesuperjunction including extending completely below the superjunction toconnect the gate and drain ends. For instance, in FIG. 6i ,superjunction 272 is surrounded below and at both gate and drain ends byLDD region 160. P-doped stripes 270 are completely separated from basesubstrate material 122, which is also positively doped, by LDD region160, which is negatively doped. As illustrated, P-doped stripes 270 arenot electrically tied to base substrate material 122, which forms thebody or substrate of MOSFET cell 250.

When MOSFET cell 250 is off, and a voltage potential is applied to N+drain contact region 180 relative to P+ source contact region 174, thePN junction between LDD region 160 and base substrate material 122depletes relatively quickly at a relatively low voltage. As the PNjunction between LDD region 160 and base substrate material 122depletes, the P-doped region of base substrate material 122 punchesthrough LDD region 160 to make electrical contact with P-doped stripes270. The electrical contact of base substrate material 122 punchingthrough LDD region 160 allows carriers from P+ source contact region 174to flow through P-channel region 170 and base substrate material 122 toP-doped stripes 270. P-doped stripes 270 and N-doped stripes 260 begindepleting once punch-through couples P-doped stripes 270 to basesubstrate material 122.

In other embodiments, illustrated in FIGS. 10a-10c and 11a-11e , P-dopedstripes are formed initially contacting the P-doped base substratematerial 122. The initial contact between P-doped stripes and thepositively doped region of base substrate material 122 improvesperformance by reducing the time before P-doped stripes and N-dopedstripes begin depleting each other. P-doped stripes immediately begindepleting with N-doped stripes when a voltage is applied, rather thanwaiting until the positively doped region of base substrate material 122punches through LDD region 160.

FIG. 10a illustrates MOSFET cell 400 with superjunction 402 whereP-doped stripes 370 extend through, or out of, LDD region 160 towardpoly gate 154 to contact base substrate material 122. P-doped stripes370 are formed under poly gate 154 using a tilted implant in oneembodiment. To form a charge balanced superjunction 402, P-doped stripes370 should have approximately the same number of positive dopant atomsas N-doped stripes 360 have negative dopant atoms. Extending P-dopedstripes 370 beyond the length of N-doped stripes 360 creates a lengthimbalance between N-doped stripes 360 and P-doped stripes 370. Thevolume of P-doped stripes 370 is increased relative to N-doped stripes360. To accomplish charge balancing of superjunction 402 with a lengthimbalance between P-doped stripes 370 and N-doped stripes 360, theconcentration of dopant atoms in P-doped stripes 370 is reduced in oneembodiment. To maintain charge balance, the product of dopantconcentration in P-doped stripes 370 and volume of P-doped stripes 370is made approximately equal to the product of dopant concentration inN-doped stripes 360 and volume of N-doped stripes 360.

As illustrated in FIG. 10a , P-doped stripes 370 are manufacturedcontacting base substrate material 122 under poly gate 154. Because basesubstrate material 122 is also positively doped, P-doped stripes 370 areinitially directly connected to the source contact of MOSFET cell 400through P+ source contact region 174, P-channel region 170, and basesubstrate material 122. N-doped stripes 360 are initially directlyconnected to a drain contact of MOSFET cell 400 through N+ drain contactregion 180 and LDD region 160. P-doped stripes 370 and N-doped stripes360 begin depleting each other on application of a voltage between thedrain and source of MOSFET cell 400, without waiting for base substratematerial 122 to punch through LDD region 160, because P-doped stripes370 are initially connected to the source and N-doped stripes 360 areinitially connected to the drain. P-doped stripes 370 and N-dopedstripes 360 form a charge balanced superjunction 402 even though thevolume of P-doped stripes 370 is increased because the dopantconcentration in P-doped stripes 370 is reduced.

N-doped stripes 360 extend to approximately the same depth, Xj, asP-doped stripes 370, and remain surrounded by LDD region 360 on each endand below. When MOSFET cell 400 is turned on by an application ofvoltage potential at poly gate 154, current flows through N-dopedstripes 360 and the portions of LDD region 160 surrounding N-dopedstripes 360.

FIG. 10b illustrates MOSFET cell 410 with superjunction 412, whichcompensates for the length imbalance between P-doped stripes 370 andN-doped stripes 360 by reducing the width of P-doped stripes 370 ratherthan the concentration of dopants. P-doped stripes 370 remain at ahigher dopant concentration, but are narrower so that the product ofvolume and charge concentration remains approximately equal betweenP-doped stripes 370 and N-doped stripes 360. Volume is calculated by theproduct of length, width, and height. Therefore, charge balance ismaintained when length is increased and width is decreased accordingly.

FIG. 10a illustrates compensating for a length imbalance by reducingdopant concentration, while FIG. 10b illustrates compensating byreducing stripe width. In some embodiments, a combined approach is used.Both the dopant concentration and width of P-doped stripes 370 isreduced. Neither the reduction of dopant concentration nor the reductionin width is enough alone to create a charge balanced superjunction, butthe width and dopant level reductions in combination approximatelybalance the total amount of charge carriers of P-doped stripes 370 andN-doped stripes 360.

Rather than modifying the dopant concentration or width of theentireties of P-doped stripes 370, the modification is localized to thearea of imbalance in some embodiments. Simply extending P-doped stripes370 toward poly gate 154 creates a charge imbalance near poly gate 154,while P-doped stripes 370 remain charge balanced with N-doped stripes360 toward N+ drain contact region 180. Therefore, any modification ofwidth or dopant concentration can be localized to the region of thesuperjunction near poly gate 154.

FIG. 10c illustrates a MOSFET cell 420 with superjunction 422. P-dopedstripes 370 extend laterally under poly gate 154. Superjunction 422remains charge balanced by a width reduction of P-doped stripes 370toward poly gate 154, with a corresponding increase in the width ofN-doped stripes 360. The cross-sectional areas of N-doped stripes 360and P-doped stripes 370 toward N+ drain contact region 180 remainapproximately equal, as with superjunction 272 in FIG. 6i . That is, thewidth of N-doped stripes 360 toward N+ drain contact region 180, Wn1, isapproximately equal to the width of P-doped stripes 370 toward N+ draincontact region 180, Wp1, and both the N-doped stripes 360 and P-dopedstripes 370 are formed to an approximately equal depth of Xj.

P-doped stripes 370 and N-doped stripes 360 are charge balanced bymodifying the stripe widths toward poly gate 154, near the lengthimbalance. That is, the width of P-doped stripes 370 toward poly gate154, Wp2, is reduced relative to Wp1, and the width of N-doped stripes360 toward poly gate 154, Wn2, is increased relative to Wn1. While alinear width gradient is illustrated connecting a first area of uniformwidths Wn1 and Wp1 to a second area of uniform widths Wn2 and Wp2, othergradient shapes are used in other embodiments, e.g., parabolic curves orright-angled steps. In some embodiments, the sloped or curved portion ofP-doped stripes 370 extends to the end of P-doped stripes 370 under polygate 154.

In other embodiments, a length imbalance is compensated for by reducingthe dopant concentration of P-doped stripes 370 in the area affected,i.e., toward poly gate 154, rather than reducing width. Dopantconcentration of P-doped stripes 370 is reduced toward poly gate 154while the dopant concentration of P-doped stripes 370 away from polygate 154 remains approximately equal to the dopant concentration ofN-doped stripes 360. The entire lengths of P-doped stripes 370 andN-doped stripes 360 include an approximately equal cross-sectional area,and the length imbalance is compensated for by a reduction in dopantconcentration of P-doped stripes 370 as in FIG. 10a . However, dopantconcentration is only reduced in P-doped stripes 370 toward poly gate154 to compensate for the length imbalance, while the dopantconcentrations of P-doped stripes 370 and N-doped stripes 360 remainapproximately equal toward N+ drain contact region 180. In otherembodiments, the length imbalance between N-doped stripes 360 andP-doped stripes 370 is compensated for by adjusting both the dopantconcentration and width of P-doped stripes 370 toward poly gate 154,while the dopant concentrations and widths of P-doped stripes 370 andN-doped stripes 360 remain approximately equal toward N+ drain contactregion 180.

FIGS. 11a-11e illustrate P-doped stripes 370 biased by an initialconnection to base substrate material 122 through the bottom of LDDregion 160, rather than through the side of LDD region 160 toward polygate 154 as in FIGS. 10a-10c . FIG. 11a illustrates a perspective viewof MOSFET cell 450 with superjunction 452. P-doped stripes 370 ofsuperjunction 452 extend deeper into base substrate material 122 thanLDD region 160. P-doped stripes 370 are initially coupled to basesubstrate material 122, which is also positively doped, by extendingthrough the bottom of LDD region 160. When MOSFET cell 450 is off, andvoltage is applied across MOSFET cell 450 between P+ source contactregion 174 and N+ drain contact region 180, superjunction 452 quicklybegins depleting because of the continuous stretch of P-dopedsemiconductor material initially connecting P+ source contact region 174through P-channel region 170 and base substrate material 122 to P-dopedstripes 370.

FIG. 11b illustrates a cross-sectional view of superjunction 452.P-doped stripes 370 extend below LDD region 160 to couple to basesubstrate material 122, while N-doped stripes 360 do not extend belowLDD region 160. In one embodiment, P-doped stripes 370 are formed usingan additional chain implantation at a higher energy than N-doped stripes360. The higher energy implantation of P-doped stripes 370 results inP-doped stripes 370 extending further into MOSFET cell 450 than N-dopedstripes 360. Similar to the length imbalance of superjunction 402 inFIG. 10a , the increased depth of P-doped stripes 370 results in animbalance between the cross-sectional area of P-doped stripes 370 andN-doped stripes 360.

To provide a charge balanced superjunction 452, the dopant concentrationof P-doped stripes 370 is reduced. With P-doped stripes having anincreased cross-sectional area, but a reduced dopant concentration, theproduct of cross-sectional area and dopant concentration isapproximately equal between P-doped stripes 370 and N-doped stripes 360.Superjunction 452 remains charge balanced even though P-doped stripes370 extend further into MOSFET cell 450 than N-doped stripes 360.

FIG. 11c illustrates MOSFET cell 460 and superjunction 462 with P-dopedstripes 370 extending down through LDD region 160, similar tosuperjunction 452 in FIGS. 11a-11b . Rather than compensating byadjusting dopant concentration, the depth imbalance of superjunction 462is compensated for by modifying the widths of P-doped stripes 370 andN-doped stripes 360. Increasing the depth of P-doped stripes 370, whiledecreasing the width, maintains P-doped stripes 370 at approximately thesame cross-sectional area as N-doped stripes 360. Therefore, N-dopedstripes 360 and P-doped stripes 370 include approximately equal dopantconcentrations and remain charge balanced. In some embodiments, a depthimbalance between P-doped stripes 370 and N-doped stripes 360 iscompensated for partially by reducing the dopant concentration ofP-doped stripes 370 and partially by reducing the width of P-dopedstripes 370.

FIG. 11d shows MOSFET cell 470 with superjunction 472, where thecompensation for depth imbalance is localized to the area of theimbalance, similar to FIG. 10c . In FIG. 11d , N-doped stripes 360 areformed using two chain implants, 360 a and 360 b, and P-doped stripes370 are formed using three chain implants, 370 a, 370 b, and 370 c. Theadditional chain implant of P-doped stripes 370 results in the depth ofP-doped stripes 370 reaching a depth approximately 150% of the depth ofN-doped stripes 360.

Implants 360 b and 370 c account for approximately equal cross-sectionalarea, and are therefore formed to approximately the same dopantconcentrations as each other to be charge balanced. The remaining twoimplants of P-doped region 370, 370 a and 370 b, are formed atapproximately half the dopant concentration of implant 360 a, becauseimplants 370 a and 370 b in total have approximately twice thecross-sectional area of implant 360 a. The upper regions of P-dopedstripes 370 and N-doped stripes 360 are formed at approximately the samedopant concentration and width, and the areas closer to the depthimbalance are formed with differing dopant concentrations or widths tocompensate for the depth imbalance. The upper regions of superjunction472 are charge balanced with each other, and the lower regions ofsuperjunction 472 are charge balanced with each other. Superjunction 472remains charge balanced as a whole.

FIG. 11e illustrates MOSFET cell 480 with superjunction 482 chargebalanced by both P-doped stripes 370 and N-doped stripes 360 extendingthrough LDD region 160 to an approximately equal depth. P-doped stripes370 and N-doped stripes 360 are also doped to approximately the samedopant concentration. Superjunction 482 remains laterally surrounded byLDD region 160. Superjunction 482 looks similar to superjunction 452 inthe same perspective view from FIG. 11a , with the primary differenceswith superjunction 452 being the depth of N-doped stripes 360 and thedopant concentration of P-doped stripes 370.

FIGS. 10a-10c illustrate biasing P-doped stripes 370 by extendingP-doped stripes 370 laterally through LDD region 160 to contact basesubstrate 122. FIGS. 11a-11e illustrate biasing P-doped stripes 370 byextending P-doped stripes 370 vertically through LDD region 160. Inother embodiments, P-doped stripes 370 are extended both laterallythrough LDD region 160 under poly gate 154, and vertically through thebottom of LDD region 160. In one embodiment, superjunction 472 ismodified so that implant 370 c extends laterally through LDD region 160under poly gate 154, while implants 370 a and 370 b are contained withinthe lateral extent of LDD region 160. In another embodiment, eachimplant of P-doped stripes 370 extends laterally through LDD region 160,and at least one implant of P-doped stripes 370 extends verticallythrough LDD region 160 as well. The volume imbalance between P-dopedstripes 370 and N-doped stripes 360 is compensated for by anycombination of the width and dopant concentration variations illustratedabove.

Biasing P-doped stripes 370 by providing initial contact through LDDregion 160 to base substrate material 122 increases performance byallowing a superjunction to begin depleting at a lower voltage fromdrain to source. Biasing P-doped stripes 370 improves performance by notrelying on base substrate material 122 punching through LDD region 160to electrically contact P-doped stripes 370. P-doped stripes 370 extendunder poly gate 154, below LDD region 160, or both under poly gate 154and LDD region 160. If N-doped stripes 360 and P-doped stripes 370 areof different lengths or depths, the imbalance is compensated for byadjusting the stripe widths, doping levels within the stripes, or both.The adjustments to the widths or the doping concentrations is designedinto the sensitive region of the superjunction where the imbalanceoccurs in some embodiments. In one embodiment, stripe widths are taperednear poly gate 154. In another embodiment, P-doped stripes 370 areformed using a spacer or tilted implant, shadowed by poly gate 154, toreduce doping levels near poly gate 154. For depth imbalance, P-dopedstripes 370 include a doping concentration that is graded with depth sothe bottom region is less doped than the regions bordering N-dopedstripe 360.

While the above discussion involves extending P-doped stripes through anN-doped LDD region of an N-channel MOSFET device, similar techniques areused in P-channel MOSFET devices by extending N-doped stripes through aP-doped LDD region to an N-doped body.

Terms of relative position as used in this application are defined basedon a plane parallel to the conventional plane or working surface of awafer or substrate, regardless of the orientation of the wafer orsubstrate. The term “horizontal” or “lateral” as used in thisapplication is defined as a plane parallel to the conventional plane orworking surface of a wafer or substrate, regardless of the orientationof the wafer or substrate. The term “vertical” refers to a directionperpendicular to the horizontal. Terms such as “on,” “side” (as in“sidewall”), “higher,” “lower,” “over,” “top,” and “under” are definedwith respect to the conventional plane or working surface being on thetop surface of the wafer or substrate, regardless of the orientation ofthe wafer or substrate.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A semiconductor device, comprising: a substrate; a lightly doped drain (LDD) region formed in the substrate; and a superjunction formed in the LDD region, wherein a portion of the superjunction extends through the LDD region.
 2. The semiconductor device of claim 1, further including a MOSFET formed in the substrate to include the LDD region and super junction.
 3. The semiconductor device of claim 1, wherein the superjunction includes: a first stripe doped with a first type of dopant and extending through the LDD region; and a second stripe doped with a second type of dopant.
 4. The semiconductor device of claim 3, wherein the first stripe includes a width less than a width of the second stripe while the superjunction remains charge balanced.
 5. The semiconductor device of claim 3, wherein the first stripe includes a dopant concentration less than a dopant concentration of the second stripe while the superjunction remains charge balanced.
 6. The semiconductor device of claim 3, wherein the first stripe includes a first dopant concentration at a first depth in the substrate and a second dopant concentration at a second depth in the substrate.
 7. The semiconductor device of claim 1, wherein the superjunction has a length with respect to a surface of the substrate, the superjunction having first and second stripes having opposite dopant types and first and second respective adjacent widths perpendicular to the length with respect to the surface of the substrate.
 8. The semiconductor device of claim 3, wherein the first stripe extends farther into the substrate than the LDD region.
 9. The semiconductor device of claim 3, further comprising: a gate over the substrate, wherein the first stripe is tapered toward the gate.
 10. A semiconductor device, comprising: a substrate; a lightly doped drain (LDD) region formed in the substrate; and a superjunction formed in the LDD region, wherein the superjunction includes a first stripe extending from a first depth in the substrate to a second depth in the substrate and a second stripe extending from the first depth in the substrate to a third depth in the substrate.
 11. The semiconductor device of claim 10, wherein the second depth in the substrate is different from the third depth in the substrate.
 12. The semiconductor device of claim 10, further including a gate formed over the substrate with a portion of the LDD region between the superjunction and gate.
 13. The semiconductor device of claim 10, wherein the first stripe extends through the LDD and the second stripe is surrounded by the LDD.
 14. The semiconductor device of claim 13, wherein the first stripe includes a width less than a width of the second stripe.
 15. The semiconductor device of claim 13, wherein the first stripe includes a dopant concentration less than a dopant concentration of the second stripe.
 16. The semiconductor device of claim 10, wherein the first stripe includes a dopant concentration gradient.
 17. The semiconductor device of claim 10, wherein the first stripe includes a width gradient. 